The current research landscape in the field of in-memory computing (IMC) and compute-in-memory (CIM) accelerators is witnessing significant advancements aimed at enhancing energy efficiency, flexibility, and performance. Innovations in analog IMC architectures are focusing on integrating shift-add capabilities directly within memory arrays, leveraging emerging non-volatile memory technologies like FeFETs. These advancements not only streamline the MAC operations but also optimize energy and area efficiency by eliminating the need for complex shift-add circuitry. On the other hand, digital CIM accelerators for spiking neural networks (SNNs) are evolving to support flexible operand resolutions and layer-wise weight/output stationarity, enabling significant energy savings and improved inference latency in edge applications. The integration of online alignment and addition algorithms in floating-point adders is also contributing to reduced area and power consumption in multi-term floating-point operations, enhancing the overall efficiency of data aggregation processes.

Noteworthy papers include one that introduces a novel FeFET-based analog IMC design with inherent shift-add capability, significantly improving energy efficiency. Another notable contribution is a digital CIM accelerator for SNNs that offers flexible operand resolution and layer-wise stationarity, achieving substantial energy savings and high classification accuracy.