Edge AI and Neuromorphic Computing Innovations

Advances in Edge AI and Neuromorphic Computing

The recent developments in the field of edge AI and neuromorphic computing are pushing the boundaries of what is possible with resource-constrained devices. Key innovations include memory-efficient training methods, precision polarization in neural networks, and the integration of analog and digital compute-in-memory (CIM) techniques. These advancements are enabling more efficient and robust AI models that can operate on microcontrollers and other edge devices.

Memory-Efficient Training: A significant trend is the shift towards memory-efficient training methods that eliminate the need for back-propagation, making it feasible to train neural networks on devices with limited memory. These methods often employ quantized zeroth-order gradient estimation and dimension reduction techniques to achieve comparable performance to traditional back-propagation-based training.

Precision Polarization: Another notable development is the precision polarization scheme, which simplifies neural network inference by using dual-level precision. This approach significantly reduces memory and computation demands by assigning low precision to most weights and activations while maintaining high precision for critical paths. This is particularly beneficial for edge devices where power and memory constraints are stringent.

Compute-in-Memory (CIM): The integration of CIM technology is revolutionizing the way neural networks are processed. SRAM-based CIM circuits, both digital and analog, are being explored to provide high computational precision and power efficiency. Hybrid architectures that combine the strengths of both digital and analog CIM are emerging as promising solutions for future neuromorphic hardware.

Noteworthy Papers:

  • Poor Man's Training on MCUs: Introduces a BP-free training scheme on MCUs, making edge training hardware design as easy as inference hardware design.
  • Neural Precision Polarization: Utilizes dual-level precision for DNN inference, significantly reducing memory and computation demands without compromising accuracy.
  • ANCoEF: Proposes an asynchronous neuromorphic algorithm/hardware co-exploration framework, achieving significant runtime speedups and energy-delay product reductions.
  • Bayes2IMC: Develops an in-memory computing architecture for Bayesian binary neural networks, leveraging nanoscale device stochasticity for efficient inference.

These innovations are paving the way for more efficient, robust, and scalable AI solutions that can be deployed on a wide range of edge devices, from microcontrollers to neuromorphic hardware.

Sources

Poor Man's Training on MCUs: A Memory-Efficient Quantized Back-Propagation-Free Approach

Neural Precision Polarization: Simplifying Neural Network Inference with Dual-Level Precision

A Review of SRAM-based Compute-in-Memory Circuits

ANCoEF: Asynchronous Neuromorphic Algorithm/Hardware Co-Exploration Framework with a Fully Asynchronous Simulator

OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs

The Inherent Adversarial Robustness of Analog In-Memory Computing

Spiking Transformer Hardware Accelerators in 3D Integration

Bayes2IMC: In-Memory Computing for Bayesian Binary Neural Networks

MANTIS: A Mixed-Signal Near-Sensor Convolutional Imager SoC Using Charge-Domain 4b-Weighted 5-to-84-TOPS/W MAC Operations for Feature Extraction and Region-of-Interest Detection

Sparsity-Aware Optimization of In-Memory Bayesian Binary Neural Network Accelerators

Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons

Architectural Exploration of Application-Specific Resonant SRAM Compute-in-Memory (rCiM)

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