The recent advancements in in-memory computing (IMC) architectures have shown significant strides towards enhancing both performance and energy efficiency. A notable trend is the integration of stochastic computing (SC) with IMC, leveraging the low computation complexity and high bit-parallel capabilities of both paradigms. This approach has demonstrated substantial improvements in performance and energy consumption, particularly in applications like neuromorphic computing and machine learning. Additionally, there is a growing focus on optimizing instruction scheduling and logic synthesis for SIMD architectures, aiming to reduce energy consumption and improve throughput. Innovative scheduling algorithms are being developed to minimize the number of memory row activations and copy instructions, which are critical for energy-efficient operation. Furthermore, advancements in SRAM-based PUF reliability prediction methods are emerging, offering new ways to estimate cell-imbalance characteristics, which can significantly impact the reliability and performance of PUF applications. These developments collectively point towards a future where IMC systems are not only more efficient but also more reliable and versatile in handling diverse computational tasks.