The field of computer architecture is moving towards addressing security vulnerabilities in cache hierarchies and improving the performance of AI hardware accelerators. Researchers are exploring new attack vectors, such as cache occupancy attacks, and developing innovative solutions to mitigate these threats. Additionally, there is a growing need for flexible and configurable fault tolerance in parallel floating-point accelerators, as well as higher-density on-chip memory for domain-specific accelerators. Noteworthy papers include: EXAM, which presents a suite of cache occupancy attacks targeting the System-Level Cache of Apple M-series SoCs, and RedMulE-FT, which introduces a runtime-configurable fault-tolerant extension of the RedMulE matrix multiplication accelerator, achieving an 11x uncorrected fault reduction with minimal area overhead. GainSight is also notable, as it provides a profiling framework for composing heterogeneous on-chip memories in AI hardware accelerators, and ForgeBench offers a machine learning benchmark suite and auto-generation framework for next-generation HLS tools.